Error Floor Estimation of Long LDPC Codes on Magnetic Recording Channels

The presence of error floor in low density parity check (LDPC) codes is of great concern for potential applications of LDPC codes to data storage channels, which require the code to maintain the near capacity error correcting performance down to frame error rates of $10^{-12}$. In order to investigate the error floor of LDPC codes under magnetic recording channels used in data storage systems, we extended the trapping set based estimation method to predict the error floor under magnetic recording channels. The goal is to accurately estimate the error rates in the error floor region for certain types of LDPC codes under the partial response channel. First, we use field-programmable gate array (FPGA) hardware simulation to find the trapping sets that cause the decoding failure in the error floor region. For each trapping set, we extract the parameters that are key to the decoding failure caused by this trapping set. Then we use a much simpler in situ simulation with these parameters to obtain the conditional decoding failure rate. By considering all the trapping sets, we obtain the overall frame error rate in the error floor region. The estimation results under the magnetic recording channel are within 0.3 dB of the direct simulation results.