Optimization for simulation of WL-CSP subjected to Drop-Test with plasticity behavior

A simulation of the Board Level Drop-Test is performed to evaluate some WL-CSP (Wafer-Level Chip-Scale Packages) performances. An elastic-plastic model is applied on both solder bump and copper pad materials. It intends to demonstrate that copper plasticity is mandatory due to the large plastic strain occuring in these materials. A statistical analysis discusses the required accuracy for the modeling analysis. This analysis is combined with a components' lifetime prediction based on a representative plastic strain. Finally, it is possible to do a relatively fast calculation while meeting the determined accuracy.