A Quasi-Parallel Encoder of Quasi-Cyclic LDPC Codes in IEEE 802.16e

We present a quasi-parallel LDPC encoder based on the quasi-cyclic characteristic of the parity check matrix of the LDPC code in IEEE 802.16e. A bidirectional recursion Arithmetic is used to improve its timing requires. The encoder is designed with simple shift registers and mod-2 adders, which is easy to be implemented in FPGA. By taking into account of some intermediate results, a low cost, high performance encoder is realized. The results show that, for the half rate LDPC code with code length 2304, the designed encoder can work at 50 MHz on Xilinx's XC3S1000 FPGA, With total equivalent gates consumes of 65964 and encoding throughput of up to kb*50 Mb/s.