Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design

The cryogenic characterization (93 K/$- \hbox{180}\ ^{\circ}\hbox{C}$ to 300 K/27 $^{\circ}\hbox{C}$) and compact modeling of a high-voltage (HV) laterally diffused MOS (LDMOS) transistor that exhibits carrier freeze-out are presented in this paper. Unlike low-voltage MOS devices, it was observed that HVMOS structures experience freeze-out effects at much higher temperatures, resulting in an output current roll-off beyond a transition temperature. Standard compact models generally do not guarantee performance below 218 K ($- \hbox{55}\ ^{\circ} \hbox{C}$), and freeze-out effects are certainly not incorporated in them. This causes the models to fail to track at lower temperatures, and designers relying on these models would be misled. In this paper, the temperature-scaling equations of the MOS Model 20 LDMOS model are modified to reflect the device operation down to 93 K, which is sufficient for designing sensor interface circuitry for lunar applications. The model is then validated against an LDMOS device designed by engineers at the Jet Propulsion Laboratory, using the IBM SiGe 5AM process. A modified parameter extraction procedure has also been developed. This generalized approach is compact model friendly and can also be implemented for other standard models. Analog circuits designed with this new model are currently being tested at the International Space Station.