A 320 Mbps flexible image data compressor for space applications

A 320 Mbps radiation-tolerant image data compression application specific integrated circuit (ASIC) chip set has been developed. The ASIC chip set implements the Consultative Committee for Space Data Systems (CCSDS) recommendation for Image Data Compression. It is applicable to both near-Earth pushbroom sensors as well as frame sensors used in exploration and deep space applications. The compressor can process sensor data in both lossless and lossy compression modes. The compression chip set implements a discrete wavelet transform (DWT) and a bit-plane-encoder (BPE). Compression modes including on-the-fly reconfiguration can be easily configured onboard potentially offering capabilities requiring integration of intelligent processing with compression. The ASIC chip set designs are implemented in 0.25um CMOS utilizing radiation-hardness-by-design (RHBD) technique. The chip set has been verified both in functions and radiation characteristics and is being qualified for a NASA mission. The measured power consumption at room temperature for the chip set is 0.17 watt/Msamples/sec with sample up to 16-bit.