FPGA Implementation of Noise Whitening Algorithm for Wireless MIMO Communication Systems

Multi-input multi-output (MIMO)techniques are of significant research interest due to their capability to dramatically increase the data rate achievable over a wireless channel without requiring additional transmit power or bandwidth. However MIMO channel impact can cause colored noise at the receiver. In this paper a hardware implementation of noise whitening algorithm is presented. The described algorithm is implemented for a 4×4 MIMO channel on a virtex-4 LX25 FPGA from Xilinx. This system completes each iteration of the algorithm in 0.5 ¿s at operating frequency of 100 MHz. the number of occupied slices on FPGA is 542 which covers 5% of the whole chip.