Low-temperature characteristics of well-type guard rings in epitaxial CMOS

Characterization and simulation of minority-carrier well-type guard rings in epitaxial substrate at 77 K were performed and compared with those at RT. The escape probability in a narrow guard-ring structure under the same amount of minority carrier injection increases by about one order of magnitude when temperature decreases to 77 K. This degradation in the guard-ring efficiency can be attributed to the enhanced drift mechanism in the conductivity-modulated layer between the well bottom junction and the epitaxial high/low junction at 77 K. In contrast, this mechanism enhances the width dependence of the escape probability at 77 K. The higher minority-carrier recombination velocity of the epitaxial high-low junction contributes to the stronger width dependence secondarily. When the epitaxial layer thickness becomes thinner, the simulation also demonstrates a stronger width dependence of the escape current as well as a reduction in its magnitude. A lightly-doped epitaxial layer on a heavily-doped substrate exhibits even more importance in the guard ring efficiency for low temperature operation, and its thickness should be kept as thin as possible.