Explanation for the Negative Differential Resistance in SOI-MOSFETs

The negative resistance region seen in the output characteristics (I
DS
(V
GS
) vs v
DS
) of silicon-on-insulator MOSFETs to be a result of the relatively poor thermal properties of the buried insulator compared with the Si-substrate. At sufficiently high power levels, the device island heats up causing degradation of the carrier mobility and a consequent limiting of the outptrt current This thermal self-limiting is also responsible for the deaparture from the ideal MOSFET ``square'' law which should be evident for these transistors having minimal ``body'' effect.