A High Performance Single Poly 0.μm BiCMOS Technology Optimized for Mixed Signal Applications

A 0.5μm BiCMOS technology optimized for mixed signal applications will be presented. The process architecture to integrate a single poly quasi selfaligned bipolar transistor in a twin well dual gate CMOS process will be described, with special emphasis on the optimization of the analogue characteristics such as the Vbe matching, linearity of the current gain and the trade-off's between gain bandwidth product, BVceo and Early voltage. Digital circuit performance is demonstrated using BiNMOS, BiCMOS and ECL ringoscillator circuits.