Engineering of the Polysilicon Emtter Interfacial Layer using Low Temperature Thermal Re-Oxidation in an LPCVD Cluster Tool

Today's high performance bipolar technologies rely upon stringent control of the polysilicon deposition and pre-deposition cleaning processes. The advent of LPCVD cluster tools allows more precise control of the interfacial layer through the use of insitu vapour cleaning and subsequent re-oxidation prior to poly deposition. In this paper, the use of thermally grown interfacial oxide layers of polysilicon emitter transistors is investigated and the results compared with an optimised process in a conventional horizontal deposition equipment. The interfacial layers are characterised by SIMS to obtain the integrated oxygen dose at the interface and by RBS to observe epitaxial realignment. The impact of the regrown interfacial oxides on the emitter and base profiles is quite small, such that the electrical characteristics are dominated by the interface properties. A process window is defined where a significant reduction of the base current can be obtained at the expense of only minor increases in the emitter resistance. It is also demonstrated how the emitter resistance and base current operafing point can be engineered using RTA annealing. Lower and upper limits for the integrated oxygen dose are defined, based on epitaxial realignment and current gain distributions. For poly deposition in a conventional furnace, the current gain can be controlled by pre-and post implant RTA temperature, while the cluster system offers an additional degree of freedom to engineer the current gain by tailoring the oxygen dose at the poly emitter interface.