Atomic Layer Engineered-Sealed Interface Local Oxidation (ALE-SILO). 0.30μm MOS Devices Isolation using a Vacuum Load-Lock Cluster Vertical Furnace

This paper will describe the characterization and electrical optimization of a high performance Atomic Layer Engineered Sealed Interface Local Oxidation (ALESILO) field isolation process steps. This process uses a vacuum load-lock equipped cluster vertical furnace (fig. 1). That allows perfectly controlled nitride/silicon interface sealing avoiding any extra RTN step[1] to achieve 100 nm range bird's beak and 0.30μm design rules SILO field isolation. A good monitoring of NMOS and PMOS devices subthreshold characteristics as well as field devices behaviour is obtained by a controlled monolayer oxidation of silicon before nitride deposition. The surface preparation condition will perfectly control the high quality of 7 nm and 5 nm thick gate oxide.