Low-skew clock distribution using zero-phase-clock-buffer DLLs

A clock distribution scheme based on a zero-phase-clock-buffer (ZPCB) is presented. Each ZPCB generates an equal phase between its input and output by adjusting its resonant frequency to slightly higher than the clock frequency. A testchip fabricated in a 40 nm LP process measures sub-psec skew over 500 MHz and 800 MHz ranges, for a 5 GHz single-ended and a 15 GHz differential ZPCB, respectively.