A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

An SSC-compliant 5 Gb/s transceiver in 65 nm CMOS is developed and tested. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase difference between the sampling clock and the signal. The phase tracking of the input signal and the data decision are performed entirely in the numerical domain.