A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications

A 90 nm 59.5 mW scalable/multi-view/H.264 multi-standard video decoder chip is implemented in a 8.53 mm
²
die. Via a throughput-efficiency architecture with reconfigurable scheduling and a cache system, a low memory bandwidth, high-throughput design is achieved. It has 3.41x throughput with 47% power reduction compared to previous work.