Comprehensive address generator for digital Signal Processing

Computational efficiency of Signal Processing Algorithm implemented in hardware depends on efficiency of datapath, memory speed, and generation of addresses for data access. In case of signal processing applications, pattern of data access is complex in comparison with other applications. If implemented in a general purpose processor, address generation for signal processing applications will require execution of a series of instructions and use of datapath elements like adders, shifters etc. In general, considerable processor resources and time are utilized. It is desirable to execute one loop of a kernel per clock. This demands generation of typically three addresses per clock: two addresses for data sample/coefficient and one for storage of processed data. A set of dedicated, efficient Address Generator Units (AGU) will definitely enhance the performance. This paper focuses on design and implementation of Address Generators for complex addressing modes required by Multimedia Signal Processing algorithms. Among other addressing modes, a novel algorithm is developed for accessing data in a Bit-Reversed order for Fast Fourier Transforms (FFT), and Zig-zag order for Discrete Cosine Transforms (DCT). When mapped to hardware, this scales linearly in gate complexity with increase in the size and uses less components.