A coalescing-partitioning algorithm for optimizing processor specification and task allocation

This paper considers the design problems of processor specification and task allocation for embedded computer systems. A graph partitioning-based representation is proposed that allows these problems to be solved concurrently. A custom design automation algorithm bared on this representation is then presented. This algorithm, named CP*-2, was benchmarked against two baseline algorithms on a combination of real and synthetic test cases with respect to two figures of merit: hardware cost and run-time. The real test cases are based on commercially developed automotive applications and the benchmark algorithms consist of heuristic and simulated annealing approaches. On average, CP*-2 was found to generate solutions with quality comparable to simulated annealing with up to an order of magnitude improvement in run-time.