Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)

The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary to suppress the parasitic leakage path and avoid the abnormal subthreshold current behavior. Second, the edge fringing field effect significantly changes the P/E speed and degrades the incremental-step-pulse programming (ISPP) slope from ideal value (=1). The complexity of the edge fringing field cannot be modeled by simple 1D tunneling, and by using 3D simulation we found that the edge fringing field greatly degrades the tunnel oxide electric field especially after electrons are programmed into the channel. Moreover, because of edge fringing field effect more charge injection is required to obtain the same memory window when the device is scaled. We propose an analytical ISPP model. A field enhancement factor (FE) is introduced, and the FE gradually decreases with electron injection while Vt gets higher. Through this model the ISPP programming of various STI structures can be well understood. Finally, we find that the self-boosting program disturb window is proportional to the ISPP slope.