A new binary tree algorithm implementation with Huffman decoder on FPGA

Compression is useful technique in digital system, as it reduces the channel bandwidths and storage size. This paper presents new Huffman decoder based on binary tree method for improving usage of memory and speed. It is shown through experiment result related to computational speed that the propose method is superior to other predecessor. The customized Huffman hardware decoder comparison is presented at different speed on various FPGA's.