Axially-doped n+-p−-n+ and p+-n−-p+ silicon nanowires: vapor-liquid-solid growth and field effect transistor characterization

Engineering materials at the nanoscale by combining controlled nanomaterial synthesis and directed assembly methods offers the potential to create new electronic and optical devices with improved performance and functionality. Semiconductor nanowires have been of particular interest as a model system for studying new physical phenomena arising from their scaled geometries as well as for applications in high performance vertical transistors, thin film electronic, electro-optical, and sensing devices and circuits. However, the use of relatively immature nanowire growth, in-situ doping, and device integration processes have made it difficult to elucidate and compare the electrical transport properties across different device platforms (e.g., nanowire versus planar) and length scales. This talk will describe recent results showing that thermally-oxidized in-situ axially-doped n
⁺
-p
^-
-n
⁺
and p
⁺
-n
^-
-p
⁺
silicon nanowires (20 to 50 run in diameter) grown by the vapor-liquid-solid technique can be used to fabricate stable and reproducible n- and p-channel top-gate and wrap-around-gate field effect transistors (FETs) that operate by inversion ofthe channel and have both high on-state current (I
_on
) and on/off-state current ratio (I
_on
/I
_off
). Control measurements using back-gated device structures that separately probe the properties of the heavily-doped source/drain regions and lightly-doped channel region confirm that radial thin film deposition on the channel is prevented during vapor-liquid-solid growth of the second heavily-doped nanowire segment, which is necessary for fabricating complementary field effect transistors using these silicon nanowires. The effective mobility estimated from the measured channel resistance of n
⁺
-p
^-
-n
⁺
and p
⁺
-n
^-
-p
⁺
silicon nanowire FETs having 1 ?m-long channels will be provided and related to planar devices. Finally, the properties of the top-gate and wrap-around-gate n- and p-channel silicon nanowire FETs will be compared as a function of global back gate bias.