Handling zero in diminished-1 modulo 2n + 1 subtraction

In this work efficient architectures of modulo 2
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+1 subtractors for diminished-1 operands which can handle zero operand are presented. The proposed subtractors have similar architecture, operate at the same speed and have the same area complexity compared to their corresponding modulo 2
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+1 adders for diminished-1 operands. Efficient modulo 2
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+1 adder/subtractor architectures for diminished-1 operands, which are welcomed in RNS applications, are also proposed.