Efficient cascaded VLSI FFT architecture for OFDM systems

This paper presents a throughput efficient cascaded FFT architecture suitable for OFDM telecommunication applications. The design exploits a technique parallelizing the radix-2 butterfly computations to increase the throughput by 2, while it keeps the complexity of the VLSI area equal to the single path delay feedback architectures. A 2048 complex point radix-2 implementation with .13 TSMC validates the results.