A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits

Partitioning algorithms are responsible for the assignment of the random logic blocks and ip blocks into the different tiers of a 3D design. Cells partitioning also helps to reduce the complexity of the next steps of the physical synthesis (placement and routing). In spite of the importance of cells partitioning for the automatic synthesis of 3D designs it has been performed in the same way as in 2D designs. Graph partitioning algorithms are used to divide the cells into the different tiers without accounting for any tier location information. Due to the single dimensional alignment of the tiers connections between the bottom and top tiers have to go through all the tiers in between, e. g., in a design with five tiers a connection between the top and the bottom tiers would require four 3D-vias. 3D vias are costly in terms of routing resources and delay and therefore must be minimized. This paper presents a methodology for reducing the number of 3D-vias during the circuit partitioning step by avoiding connections between non-adjacent tiers. Our algorithm minimizes the total number of 3D-vias while respecting area balance, number of tiers and I/O pins balance. Experimental results show that the number of 3D-vias was reduced by 19%, 17%, 12% and 16% when benchmark circuits were designed using two, three, four and five tires.