Programmable hybrid co-processor for real-time image understanding

A novel hybrid image co-processor architecture that utilizes analog and digital computing techniques cooperatively is described. The chip computes stereo and motion correspondence at a rate of 30 frames/sec. This feature combined with programmable capabilities of a conventional processor makes it possible to execute in real-time many powerful yet so far underutilized computing techniques such as multiresolution or image pyramid processing. The overall system is designed to be compatible with existing computer architectures to allow for commercial product development in the near future. Additional benefits of the system over existing image processing methods are multiple programmable configurations, increased processing speed, low power consumption, reduced size and cost.