Optimization of sample/hold circuit for high-speed and high-resolution ADCs

A sample/hold (S/H) circuit for a 14 bit 100 MSample/s analog-to-digital converter is implemented and optimized. High performance gain-boosted folded-cascode opamp (GBFCA) and bootstrapped switches are used to maximize SNDR and SFDR of the S/H circuit. An optimal design criterion is developed to find the best solution giving the shortest settling time. After eliminating the slow-settling component in signal path, the sample S/H circuit achieves 5 ns settling time to 0.001%, 81.2 dB SNDR and 100 dB SFDR for 10 MHz input signals.