Near-optimum switched capacitor sample-and-hold circuit

Performance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13 ¿m CMOS technology featuring a signal to noise and distortion ratio (SNDR) of -75 dB at 12 Ms/s for a 1 Vpp output voltage. Theoretical calculations and experimental results are also given to demonstrate its validity.