Full custom design of comparators for LDPC decoder

Comparator is the key module in LDPC decoder that consumes most of the power and area. In this paper, a new comparator based on pass transistors and dynamic logic is proposed to decrease the power and the area. The comparator is implemented with full custom design at SMIC 0.18 1P6M technology. The simulation result of layout shows that the power drops by 11.4% and the area is reduced by 30% compared with the circuit mentioned in reference which we implement with the same technology.