Development and code partitioning in a software configurable processor

Most reconfigurable processors are not fully controlled by software; they are reconfigured using hardware description languages. By moving the data paths into the processor, the system architect can discard the external control logic, the finite state machines and micro-sequencers. Examples for such a processor are the members of the Stretch family, Software Configurable Processors which have a reconfigurable fabric embedded inside the actual processor. This allows development in a high level programming language like C. The paper provides an overview of the architecture and a case study problem based on the 2D FFT illustrating the issue of software-hardware partitioning. A software only solution is first described and is used as a benchmark to compare two code partitioning schemes proposed later. The designs of the partitions are described in detail along with their time analyses. The primary criterion chosen is the overall execution time along with the frequency at which the reconfigurable fabric can be clocked. By comparing the results it can be concluded as to which partition performs better and the parameters that contribute to reduction in execution time. This paper also provides an overview of the challenges and benefits of software reconfigurable processors.