A CMOS low-dropout regulator with high power supply rejection

A CMOS low-dropout regulator (LDO) with high power supply rejection (PSR) characteristics is presented in this paper. By utilizing an optimized error amplifier, which feedforward the supply ripples into the gate of power transistor so as to maintain a constant gate-source voltage in power transistor under supply ripples, the proposed LDO provides high PSR capability. A prototype of the LDO has been implemented in 0.6 ¿m double poly, double metal, CMOS technology, the die size is 650 ¿m × 600 ¿m. Experiment result shown that the PSR is -62.9 dB @ 1 kHz, -51.5 dB @ 10 kHz and -37.9 dB @ 100 kHz, respectively. The LDO provides 150 mA maximum output current, while consumes 20 ¿A quiescent current, with a dropout voltage of 120 mV @ 100 mA. The total error of the output voltage due to line and low variation is less than ±0.1%, and the temperature-coefficient is 65 ppm/°C.