An 8-b 600MSmaples/s folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC) with Current Mode Logic (CML). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. To ensure high speed and low noise, the CML is used. The circuit is implemented in a 0.18-¿m CMOS technology, and measures 1.5 mm × 1.5 mm (including pads). The simulation results illustrate a conversion rate of 600 MSamples/s and a power dissipation of less than 150 mW.