On the VLSI Implementation of low complexity K-best MIMO decoders

The VLSI implementation of maximum likelihood (ML) detection for higher order multiple input multiple output (MIMO) systems continues to be a major challenge. Battery driven handheld devices impose strict area and power constraints while demanding guaranteed performance over a wide range of operating conditions. This paper presents a modified, low complexity K-best detector for a 4×4, 64 QAM MIMO system , which uses a modified path extension algorithm to bring down the computational complexity by more than 50%. It also exploits the structure of a QAM constellation to achieve low power operation by reducing the number of costly multiplication operations while computing the path metrics. The two new approaches, combined with a resource shared architecture leads to the implementation of a very efficient FPGA based system, where we verify the performance of the algorithm.