A 5.5-GHz 3mW LNA and inductive degenerative CMOS LNA noise figure calculation

This paper, presents a precise noise figure formula for inductive degeneration CMOS LNAs. Also a fully integrated CMOS LNA with on-chip spiral inductors in 0.18µm CMOS technology for 5.5-GHz unlicensed national information infrastructure (U-NII), 802.11a and IEEE 802.11n wireless LAN Receivers is presented in this paper. Using a cascode current reuse structure with inter-stage inductors we achieved low power consumption and high power gain. We proved that the interstage inductors must be designed with a new method compared to newly published papers. This structure is based on two cascode configuration which provides a good output swing thus allowing the integration in low voltage technology. This configuration also permits good input impedance matching, low noise figure and high reverse isolation. Complete simulations of the circuit at 5.5-GHz center frequency, have shown that the circuit has 3.1dB NF, 1.2GHz 3dB power bandwidth, 20.63dB power gain (S21), high reverse isolation (S12)≪−45dB, −29.4dB input matching (S11), −25dB output matching (S22), and −15.9dBm 3rd order input intercept point (IIP3). The power consumption is 3mW at 1.8V supply voltage.