Theory and Operation of Space-charge-limited Transistors with Transverse Injection

The development of a new device, called the space-charge-limited (SCL) transistor with transverse injection is reported in this paper. A theoretical model for space-charge-limited transistors, both npn and pnp, on high-resistivity silicon substrates is described and a quantitative analysis is given. Experimental results for SCL transistors are presented to support the model's validity. According to the model, current in SCL transistors is controlled by the base of a parallel-connected lateral transistor in two ways. First, the base of the parallel transistor controls the potential step in the high resistivity base of the SCL transistor. Second, the base of the parallel transistor injects carriers in the direction transverse to the SCL current flow. These carriers are of types opposite to those that carry the current flow in the SCL transistor and thus partly neutralize the space-charge in the current flow. The carriers propagate, predominantly by drift, across the high-resistivity base region of the SCL transistor. The resulting base transit time is about two orders of magnitude faster than that of a bipolar transistor with equal base width. No charge storage takes place in saturation. These features and the very low device capacitances make the SCL transistor attractive for low-power, fast-switching applications. Current gains as high as 70,000 are obtained at low current levels. The current gain decreases at higher current levels because the parallel lateral transistor turns on. It is also demonstrated that complementary pairs of SCL transistors can be fabricated with three masking steps, including metalization.