Implanted Source/Drain Junctions for Polysilicon Gate Technologies

Shallow (< 1.0-µm) n
⁺
-p junctions are required for dense dynamic FET memory. Ion implantation is a natural technology to fulfill the geometric requirements of shallow highly doped n
⁺
regions in a dual polysilicon gate IGFET technology. However, implantation of
³¹
P and
⁷⁵
As at high dose levels severely damages the crystal lattice and subsequently is difficult to anneal. This tends to make implanted junctions more leaky than their diffused counterparts and causes them to have lower apparent reverse breakdown voltages. The detrimental effect of residual end of process damage, resulting from the implantation, is correlated to the electrical characteristics of the n
⁺
-p junction. A junction process technology is described that can provide leakage levels of less than 0.25 fA/µm
²
(25 nA/cm
²
), sharp reverse I–V characteristics, and junction depths of 0.25 to 1.0 µm.