Flexible oblivious router architecture

In this paper we present a router architecture that accommodates a family of oblivious routing algorithms. The architecture is suitable for current technologies, and it is intended for multiprocessor and massively parallel systems. Via the proposed architecture, we suggest that general-purpose routers can be designed to accommodate a variety of multiprocessor interconnection networks. In particular, the routing algorithms of those interconnection structures that can be classified as trees, cubes, meshes, and multistage interconnection networks can be accommodated with a flexible, easily implemented architecture. Our investigation strongly suggests that a common design can satisfy at least forty network topologies with the introduction of a few instructions that are very simple to implement. The overall conclusion is that general-purpose cost-effective routers can potentially be designed that perform equally as well as customized routing logic, suggesting the possibility of a common router for multiple interconnection networks. Furthermore, the proposed architecture provides programming capabilities that allow other oblivious routing algorithms not considered in our investigation to be accommodated.