Designer-level verification using TIMEDIAG/GENRAND

TIMEDIAG/GENRAND is a tool set used on various portions of the CMOS processor for the IBM S/390® Parallel Enterprise Server Generation 4 to assist in designer-level logic verification. The concept of surrounding the logic design (hereafter referred to simply as “logic”) under test with irritator behaviorals, a methodology developed and proven effective on larger simulation models, is moved to the designer level without the overhead of writing multiple behaviorals. Rather than writing source-level (e.g., VHDL, C code, etc.) behaviorals, the method creates an external stimulus to the design by using a series of generalized timing diagrams that obey the interface protocols of the logic under test. These timing diagrams are entered using the TIMEDIAG (timing diagram) editor. The effort required for logic verification is thus limited to understanding and laying out the interfaces to the design—a task that must be done for any well-designed unit of logic, regardless of whether or not it is being verified at the designer level. Once the timing diagrams are written, GENRAND (general random driver) is invoked to run simulation on the design. GENRAND randomly initiates the timing diagrams that obey the interface protocol, causing many different input and output permutations. This simulation is very effective in testing the logic implementation.