A new architecture for high performance intra prediction in H.264 decoder

This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard. Our goal is to design an intra prediction engine for 4K×2K@60fps ultra high definition (UHD) decoder. The proposed architecture can provide very stable throughput, which can process any H.264 intra prediction modes within 66 cycles. Compared with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The intra prediction engine is divided into two parallel pipelines, one is used for block prediction loops and the other is used to prepare data for MB loops. The proposed architecture can overlap data preparing time with prediction time, which can finish data loading and storing within 2 cycles pipeline stalls. We apply the combined module approach to achieve high throughput and low area cost for ultra high-definition video, which is based on a novel organization of the intra prediction equations. The proposed architecture is verified to work at 84 MHz in a Xilinx V4 FPGA. It costs about 28.7K gates by using TSMC 90nm and satisfies requirement of our UHD decoder.