Nanoscale TiN wet etching and its application for FinFET fabrication

It is well known that the PVD TiN is a promising gate material to set symmetrical threshold voltage (V
th
) for nondoped channel FinFET CMOS thanks to its midgap work function [1–4]. One of the most important issues in the TiN gate FinFET fabrication is the TiN gate formation especially the TiN etching on the sidewalls of the tall fin channels by using conventional RIE. Hence, an isotropic TiN etching technique is strongly required in the tall FinFET fabrication. In this paper, we experimentally investigate nanoscale TiN side-etching by wet process and demonstrate the FinFET CMOS fabricated by using the developed TiN wet etching technique.