A 42 mW 2 GS/s 4-bit flash ADC in 0.18-μm CMOS

A low power 4-bit 2 GS/s flash ADC is presented. To enhance the speed, the analog part of the ADC is fully pipelined; reset switches are inserted into preamplifiers and comparators for fast overdrive recovery. Post-simulation results show that the peak DNL and INL are 0.04 LSB and 0.06 LSB, respectively. With 970.2 MHz input, the SFDR and ENOB achieve 33.2 dB and 3.61 bits at 2 GS/s. the ADC occupies 0.32 mm
²
active area in 0.18-μm CMOS process and consumes 42 mW with a 1.8 V power supply.