FPGA-Based Parallel Pattern Matching Algorithm for Network Intrusion Detection System

Pattern matching is the critical part in network intrusion detection system (NIDS). Fast pattern matching algorithm is the key to improve the system performance. In this paper, a fast reverse pattern matching algorithm and the hardware implementation suitable with field programmable gate array (FPGA) are proposed. Taking advantage of the parallelism and programmability of FPGA, this design reduces the pattern match delay greatly. This design is implemented in a NetFPGA platform, which is an open hardware platform optimized for high-speed network. The parallel pattern matching system provides a high throughput of 4 Gbps with no data loss, which proves the information processing rate of this design.