Implementation of digital HDTV video decoder by multiple multimedia video processors

A digital HDTV video decoder system is designed and implemented by using multiple multimedia video processors in a loosely-coupled multi-processor architecture. This decoder system can decompress video bitstream up to 20 Mbits/s and produce analog output at HDTV pixel rate. This design has the advantage of hardware scalability to adapt different picture resolutions and computation requirements. The design target is the video subsystem of a digital HDTV receiver.