Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits

This paper presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8 mm a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10 V) and very low voltage (7 V), followed by a 200 second voltage stress at 30 V. Seven unreliable CUT that escape nominal voltage (NV) testing are successfully caught by VLV testing and there is no CUT that is caught by NV testing but escapes VLV testing. The results indicate that VLV testing is more effective than NV testing in screening out unreliable a-Si TFT circuits.