CMOS low-VT preamplifier for 0.5-V gigabit-DRAM arrays

A novel CMOS low-V
_T
preamplifier suitable for low-voltage and high-speed mid-point sensing was developed for gigabit DRAM. This preamplifier consists of a low-V
_T
NMOS cross couple, a low-V
_T
PMOS cross couple and a high-V
_T
CMOS latch. The sensing speed of the proposed preamplifier at data-line voltage of 0.5 V is 62% higher than that of a conventional preamplifier. By activating the low-V
_T
NMOS and PMOS cross couples temporarily during write operation, writing time is 72% shorter compared to the case with the high-V
_T
CMOS latch only. Data-line charging current of a memory cell array with the proposed preamplifier is reduced by 26% by decreasing data-line voltage from 0.8 to 0.5 V.