Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations

Design guidelines for velocity-saturated, short-channel CMOS drivers are presented in this paper based on approximating the package inductance by an effective, lumped, power-supply bus parasitic inductance. A worst-case maximum simultaneous switching noise V/sub GM/ and gate propagation delay time t/sub D,1/2/ are treated as performance constraints for which driver design tradeoffs between driver geometry, the maximum number of simultaneously switched drivers, and the effective inductance are obtained. For typical loading conditions, design examples based on the proposed guidelines are shown by SPICE simulations using the MOS3 model to agree with both design goals within 10%.