3.5 Gb/s/spl times/4-Ch Si bipolar LSIs for optical interconnections

The transmitter and receiver LSIs described here include a 5-to-1 multiplexer, 1-to-5 demultiplexer, optical interface and analog phase-locked loop (PLL) circuits that generate 3.5 GHz clock and retimed data. The chips make it possible to connect twenty pairs of 700 Mb/s electrical ports (14 Gb/s throughput) through four fibre channels without external elements even for the PLL.