Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC

An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a 150 MS/S sampling rate and dissipating 34 mW power. It is based on integer division circuits that are arranged in a binary tree structure. We emphasize on the digital calibration method of such an ADC in order to extend its operational temperature range and correct the effect of mismatch and process variations. The calibration is achieved by controlling the voltage supply of the root divider and the amplification and offset correction of the residue that is produced by this divider.