Power comparison of an asynchronous and synchronous network on chip router

This paper presents an asynchronous and a synchronous NoC router architecture. The asynchronous scheme is implemented by the help of CSP-Verilog language and the synchronous one is designed employing VHDL language. Their designs are similar except the extra links which are in charge of handshaking processes in asynchronous architecture. According to the experimental results the transition counts of buffer, and switch components in synchronous router are almost 82% and 60% of asynchronous one, respectively. On the other hand, the transition counting of routing unit in asynchronous NoC router is nearly 73% of synchronous one. Power consumption of them are evaluated according to the obtained transition counting. Based on the comparison the power consumption of buffer and switch components are almost same due to their similar structure. However, the power consumption of routing unit component in asynchronous design is lower than synchronous one.