Active circuit to through silicon via (TSV) noise coupling

In this paper, we propose a coupling model between through silicon via (TSV) and substrate based on a 3-Dimensional transmission line matrix (3D-TLM), which utilizes equivalent lumped circuit model of silicon substrate and TSV. The proposed model is verified by S-parameter simulations using a 3D field solver and analyzed with various structural parameters: TSV diameter, distance between TSV and noise source, and silicon substrate height. Based on the model, timing jitter degradation on phase locked loop (PLL) caused by substrate noise coupling is investigated. A shielding technique using a guard ring structure is applied to suppress the coupling noise.