A DSP architecture optimized for wireless baseband

The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations such as LTE. The Tensilica ConnX Baseband Engine processor core implements a 3-issue VLIW, 8-way SIMD architecture. It can perform 16 multiply-add operations per cycle, and executes a full radix-4 FFT butterfly or 4 complex FIR filter taps per cycle. It directly implements vector division and reciprocal square root operations. At 400 MHz, it provides almost 13 GB per second of memory bandwidth. The rich programming environment, including vectorization of scalar C applications, allows easy deployment into cellular base-station, femto-cell and other software-agile radio applications, and into multi-standard broadcast receivers.