Low-jitter fractional spread-spectrum clock generator using fast-settling dual charge-pump technique for Serial-ATA application

A low-jitter fractional spread-spectrum clock generator (SSCG) by utilizing a fast-settling dual charge-pump (CP) technique has been developed for Serial-ATA (SATA) applications. The proposed fast-settling dual CP technique not only reduced a design area but also shortened settling-time by controlling the CP operation sequence in an SSCG settling period. A multi-modulus divider using differential dynamic flip-flops was applied to our SSCG to reduce the design area, power consumption, and jitter. The proposed SSCG for SATA generation I was fabricated in a 0.13 mum CMOS process. The settling-time was 3.91 mus faster than that of a conventional SSCG, 8.11 mus. The random jitter and total jitter in 250 cycles at 1.5 GHz were 2.7 psrms and 3.3 psrms, respectively. The EMI reduction that meets SATA specification was 10.0 dB. The design area and the power consumption were 300 times 700 mum
²
and 18 mW, respectively.