Composition Effects of $\hbox{Ti}_{x}\hbox{Ta}_{y}$ Dual-Doped $\hbox{HfO}_{x}/\hbox{SiO}_{2}$ Stacked Dielectrics on Electrical and Reliability Characteristics of Advanced Metal-Oxide-Semiconductor Capacitors

Metal-oxide-semiconductor (MOS) capacitors with metal-gate/high-
k
dielectric stacked films are a promising candidate to provide enhanced device performance. To study these issues, a comparative study of the composition effects of Ti
_x
Ta
_y
dual-doped HfO
_x
/SiO
₂
stacked films as gate dielectrics of advanced MOS capacitors has been investigated. The related degradations of various Ti
_x
Ta
_y
dual-doped HfO
_x
/SiO
₂
stacked dielectrics have been investigated under various postdeposition annealing (PDA). The results indicate that, by developing a proper composition with Ti
₁
Ta
₃
dual doped in a HfO
_x
/SiO
₂
stacked dielectric, enhanced electrical and reliability characteristics, including equivalent oxide thickness, leakage current density, hysteresis, interface trap density, stress-induced flatband-voltage shift, stress-induced leakage current (SILC), and defect generation rate, were demonstrated. The mechanisms related to a larger barrier height formed at the Si/dielectric interface, an induced more negative charges, and a more significant crystalline retardation characteristic can be attributed to a suitable Ti
_x
Ta
_y
dual-doped HfO
_x
/SiO
₂
dielectric. Better reliability properties can be obtained by a suitable Ta content incorporated into the dielectric bulk. More Ti incorporated into the gate dielectric bulk can result in more significant charge trapping. Reliability degradation related to the SILC of capacitors can be attributed to the interface-trap-assisted tunneling at low electric fields.